1. Field of the Invention
The present invention relates to a power supply device control circuit, a power supply device, and a control method for the same.
2. Description of the Related Art
As up-to-date ICs (integrated circuits) have been improved in the integration and reduced in the source voltage, they are demanded for being lowered and minimized in the power consumption. Also, with the source voltage becoming reduced, the threshold voltage of MOS transistors in each IC is lowered. As the threshold voltage is lowered, its sub threshold area will be declined in the characteristic of current interruption. This may hence cause a current to be leaked during the off state where no voltage is applied between the gate and the source of a MOS transistor. Although the power consumption is successfully lowered and minimized, the effect of current leakage will hardly be eliminated.
For attenuating the current leakage at a MOS transistor where the threshold voltage is lowered, a technique is known of controlling the backgate voltage. According to the technique, by modifying the back gate voltage deeply at the off state, the characteristics of current interruption in the sub threshold area can be improved. The action of deeply modifying the back gate voltage means that when the transistor is of NMOS type, a voltage lower than that at the source is applied to the P substrate. When the transistor is of PMOS type, a voltage higher than the source voltage is applied to the N substrate. In the MOS transistor, while the back gate voltage is shallowly modified to maintain the on state with a low threshold voltage, the current leakage can be minimized during the off state where no voltage is applied between the gate and the source.
Such a power supply device having the above described IC is designed to connect with a variety of electronic apparatuses which are different in the voltage requirement and thus includes a plurality of DC/DC converters (as disclosed in Japanese Unexamined Patent Publication Nos. 2003-61341, 2005-210884). The power supply device having the described IC may be arranged to detect the power efficiency of each of the DC/DC converters and when any DC/DC converter is found having its power efficiency lower than a predetermined setting level, cancel the action of the DC/DC converter (as disclosed in Japanese Unexamined Patent Publication No. 2003-333833).
A power supply device 100 shown in FIGS. 4 and 5 includes a plurality of DC/DC converters 120 to 140 and is connected to an external device 200. The power supply device 100 supplies the external device 200 with a source voltage VCC, gate voltages VBGP and VBGN to be supplied to the back gate of its MOS transistor, an input/output voltage VIO, and other voltages VXX. The power supply device 100 exchanges a variety of data carried on the control signal (IIC) with the external device 200. The external device 200 consists of one or more integrated circuits.
The power supply device 100 includes an interface controller 150 as shown in FIG. 5. The interface controller 150 is connected with a bus B1. The external device 200 includes such a NAND circuit 210 as shown in FIGS. 5 and 6. The DC/DC converters 120 to 140 in the power supply device 100 are arranged to modify the source voltage VCC to be supplied to the NAND circuit 210, the back gate voltage VBGP to be supplied to the back gates of the PMOS transistors FET10 and FET30 in the NAND circuit 210, and the back gate voltage VBGN to be supplied to the back gates of the NMOS transistors FET20 and FET40 in the NAND circuit 210 respectively. Denoted by X and Y in the drawings are input terminals to which a high level signal or a low level signal is supplied and denoted by Z is an output terminal.
For example, when its interface controller 150 receives an action command signal from an external device connected to the interface controller 150, the power supply device 100 instructs the register REG0 to store the action command signal. When the action command signal carries a stop command, the action of the DC/DC converters 120 to 140 is canceled. When the action command signal carries an action command, the DC/DC converters 120 to 140 are activated.
When its interface controller 150 receives a voltage operation signal for the source voltage VCC from an external device connected to the interface controller 150, the received voltage operation signal is stored in the register REG1 and an analog voltage signal (reference voltage) corresponding to the voltage operation signal is inputted via a D/A converter DAC1 to an error amplifier ERA1. Then, the power supply device 100 drives the error amplifier ERA1 to compare a feedback of the source voltage VCC with the reference voltage and thus controls so that the source voltage VCC is close to the reference voltage. Also, when its interface controller 150 receives voltage operation signals for the gate voltages VBGP and VBGN from an external device connected to the interface controller 150, the power supply device 100 instructs the error amplifiers ERA2 and ERA3 to modify the back gate voltages VBGP and VBGN, which are supplied to the back gates of the MOS transistors FET10 to FET40, to be close to their reference levels in the same manner as of the error amplifier ERA1 controlling the source voltage VCC to its reference level. Accordingly, the power supply device 100 allows the DC/DC converters 120 to 140 to modify the voltages VCC, VBGP, and VBGN to their respective optimum levels independently in response to the action command signals and the voltage operation signals received at its interface controller 150.